The present invention relates in general to the processing of materials, and more particularly semiconductor substrates for use in electronic, optic and optoelectronic components. More specifically, the invention relates to a process for cleaving two layers of a wafer along an embrittled or weakened zone between the two layers, wherein the process includes a thermal anneal for the purpose of cleaving the layers.
Processes of the aforementioned type are already generally known. In particular, the skilled artisan is aware of how to utilize such known processes in order to produce cleavage of the layers. Generally, a layer is cleaved from the substrate along a weakened zone that has been previously created by the implantation of species within the substrate. The implanted species may be ions or atoms. Thus, it is known to implant a substrate of a semiconductor material such as silicon with ions or atoms of hydrogen or helium to provide this weakened zone.
The weakened zone is determined with respect to the nature of the material, the nature of the species implanted and the energy of implantation. Generally, the weakened zone is in the form of a plane that is oriented essentially parallel to the implantation surface of the substrate.
It is likewise possible to produce the weakened zone by other means known in the art, for example by constructing an intermediate region of porous material between two regions of dense material, by forming an oxide layer embedded in a substrate (for example a Silicon On Insulator (“SOI”) substrate), or by bonding together two layers wherein the bonding area provides the weakened zone.
The cleaving of a layer along a weakened zone can be used to obtain thin layers, the thickness of which may range between a fraction of a micron and several microns, as described, for example, in U.S. Pat. No. 5,374,564. This document describes a process known by the name SMARTCUT® which is used to manufacture SOI structures. The main steps of SOI manufacturing according to this process are as follows:                Oxidation of an upper silicon plate in order to create an oxide layer (which corresponds to the embedded oxide layer of the SOI structure),        Implantation of ions into the upper plate for the purpose of creating a weakened zone, and to delimit, on the one hand, by means of this zone, the SOI structure (situated on the side of the embedded oxide) and, on the other hand, a silicon material,        Bonding of the upper plate onto a supporting plate which may be made of silicon or of another material,        Cleaving of a layer, preferably by annealing the structure, for the purpose of:                    cleaving on one hand a SOI structure comprising the supporting plate, the embedded oxide layer and the silicon layer situated between the embedded oxide and the weakened zone and, on the other hand, the silicon material situated on the other side of the weakened zone. In addition, upon completion of the cleaving process, cohesive forces may still exist between the two layers, which thereby remain integral with one another.            Detaching the two layers, i.e., by physically disconnecting them, during or after the thermal anneal,                        Additional treatment intended to reduce the surface roughness of the SOI resulting from the cleaving and detachment processes.        
Hereinafter within this text, the structures to be treated and the layers constituting them that are to be detached will be designated by the generic term “wafer”. The term “donor wafer” will also be used to designate the material from which the wafer layers are to be cleaved and will include both single materials, e.g., silicon, as well as composite or bonded structures of two or more different materials or components, such as a base wafer of one material that is bonded to a substrate or support of a different material.
The surface condition of the wafers is an extremely important factor, as very stringent specifications are imposed with respect to the subsequent use of the wafers following the detachment process, for example, when semiconductor material is used to form electronic, optical or optoelectronic components. This surface condition is characterized, in particular, by the surface roughness of the wafers following detachment. It is therefore common to find specifications for roughness that should not exceed 5 Angströms expressed as a RMS (or Root Mean Square) value. The measurements of roughness are generally made with an atomic force or AFM microscope. With this type of device, the roughness of surfaces scanned by the tip of the AFM microscope is measured, ranging from 1×1 μm2 to 10×10 μm2 and more rarely up to 50×50 μm2, or even 100 ×100 μm2.
It is also made clear that it is possible to measure the surface roughness using other methods, in particular by means of a “haze” measurement. In particular, this method has the advantage of making it possible to quickly characterize the uniformity of the roughness over an entire surface area. This haze, measured in ppm, is the result of a method which utilizes the optical reflection properties of the surface being characterized, and corresponds to an optical “background noise” diffused by the surface due to its microroughness.
An example of the relationship between haze and roughness, in the case of the surface of a conventional SOI, is illustrated in FIG. 1. It is indicated that the haze measurements that will be provided in this text are taken according to the same protocol and by means of the same device, in this case an instrument of the KLA Tencor Surfscan SPI® type.
It is likewise indicated that a SMARTCUT®-type process can also be used to form structures other than SOI structures, for example Silicon On Anything (“SOA”) or even Anything on Anything (“AOA”) structures. Cleaving and detachment anneals are conventionally carried out in annealing furnaces a typical configuration of which is illustrated in FIG. 2. Furnaces such as this are capable of simultaneously processing a plurality of wafers. FIG. 2 thus shows a plurality of wafers 10 arranged on a receptacle 11 such as a quartz boat, the wafers being aligned in parallel. The boat 11 is itself place on a loader 12 fastened to a door 13 for sealing the mouth of the furnace. The assembly 100 formed by the door 13, the loader 12 and the boat and the wafers supported by the loader is capable of moving in relation to an furnace structure 20 which comprises a quartz processing tube 21 around which a heating element 22 is wound. A pyrometer tube 23 equipped with thermocouples is likewise provided.
The furnace of FIG. 2 is shown in open position. In a closed position, the assembly 100 is inserted into the furnace structure 20, the door 13 blocking the mouth of the furnace.
Inside of each wafer to be detached, the two layers forming the wafer face each other so that the useful surfaces, for which it is desired to control the surface condition in an extremely precise manner, are placed face-to-face. Therefore, it is particularly important to take measures to ensure the best possible surface condition (specifically roughness) for these useful surfaces.
Returning to the prior art illustrated in FIG. 2, the wafers to be detached are therefore arranged vertically. In this way, the two layers of each wafer being detached are prevented from moving and do not move in relation to one another (specifically following the detachment process, when the detached layers are removed from the furnace).
A relative movement of the two layers such as this might actually run the risk of producing scratches on the surfaces of the detached layers. And it is likewise very important that the surface condition (and in particular the roughness) of these layers be as even as possible, on the surface of the layer.
FIG. 3 illustrates the surface roughness of a SOI wafer after detachment, following a cleaving anneal that has been carried out in a conventional manner in an annealing furnace, such as that shown in FIG. 2. The roughness is represented by means of a haze measurement. This FIG. 3 illustrates a dissymmetry in the roughness of the SOI structure, which corresponds to a lower haze 25 on the part of the SOI structure located at the bottom part of the furnace, which is the so-called “notch” of the SOI structure that is placed on the bottom during annealing. It is shown as being situated to the left, at 9-o'clock in FIG. 3.
Thus, it appears that if known detachment anneals actually make it possible to prevent movements capable of leading to the formation of scratches, they promote irregularities in the surface roughness of the layers resulting from the detachment process. This constitutes a disadvantage that is now remedied by the present invention.